1. Field of the Invention
The present invention relates generally to integrated circuits, and more specifically to a method for forming interconnect lines in integrated circuits.
2. Description of the Prior Art
As integrated circuit devices become more complex, greater numbers of interconnect levels are required to connect the various sections of the device. Complex devices are being designed which have two or more levels of interconnect. These levels of interconnect are typically made of polycrystalline silicon or metal. When multiple layers of interconnect are used in this manner, difficulties are encountered in forming upper interconnect levels because of uneven topographical features caused by lower interconnect levels. Thus, topography of interconnect layers affects the ease of manufacturing of the integrated circuit device.
The uneven topographical features of multiple interconnect levels are caused by forming the various interconnect layers above each other, resulting in the creation of hills and valleys on the surface of the device. Those skilled in the art will recognize it is difficult to get upper interconnect layers to cross over the hills and fill in the valleys created by the underlying interconnect layers. These step coverage problems can result in voids and other defects in the interconnect signal lines themselves, and in the contact vias formed between interconnect signal lines.
In order to make forming upper interconnect levels easier, planarization of lower interconnect levels is routinely performed. Typically, a layer of material such as a reflow glass or spin on glass can be used as part of an interlevel dielectric layer. These materials, when applied properly, have an upper surface which is smoother and more nearly planar than the topography of the underlying surface. This allows the roughness caused by underlying interconnect layers to be smoothed out somewhat prior to the formation of the next layer of interconnect. This next layer of interconnect is then formed on top of the planarized interlevel dielectric layer. Even with this technique, step coverage problems exist since formation of the interconnect layer on the planarized dielectric layer generates uneven topographical features for the next dielectric layer, requiring further planarization. In addition, the planarization improves the flatness of the surface, but does not completely eliminate hills and valleys caused by underlying topographical features.
Therefore, it would be desirable to provide a method for forming interconnect lines which are free of voids and other defects, and which result in a more planar topography. It is also desirable that such a method does not significantly increase the complexity of the manufacturing process.